I/O Hardware Concepts
To manage I/O, an Operating System must understand how the CPU physically communicates with peripheral devices. This communication happens through a combination of electrical buses, specialized registers, and signaling protocols.
The Interface: Ports and Registers
A device controller typically exposes its functionality to the CPU through a small set of storage locations called registers. There are four standard registers found in almost every I/O interface:
| Register | Purpose |
|---|---|
| Data-In | Read by the CPU to get data from the device. |
| Data-Out | Written by the CPU to send data to the device. |
| Status | Contains bits that indicate the device's state (e.g., Busy, Error, Data-Ready). |
| Control | Written by the CPU to start a command or change a device mode (e.g., 'Begin Read'). |
I/O Addressing Models
The CPU needs a way to 'address' these registers. There are two primary architectural models for this:
- Memory-Mapped I/O: The device registers are mapped into the same address space as RAM. The CPU can use standard memory instructions (like `MOV` or `LDR`) to talk to the hardware. This is common in modern architectures like ARM.
- Isolated (Port-Mapped) I/O: The CPU uses a completely separate address space and dedicated instructions (like `IN` and `OUT` in x86) specifically for I/O ports.
Polling: The Simple Handshake
In a polling (or programmed I/O) operation, the CPU and Controller engage in a simple loop:
1. CPU reads the Status Register repeatedly until the 'Busy' bit is cleared. 2. CPU writes data into the Data-Out Register. 3. CPU sets the 'Command-Ready' bit in the Control Register. 4. Controller sets the 'Busy' bit and performs the physical I/O. 5. Controller clears the 'Busy' bit once finished.
This is called 'Busy Waiting' because the CPU cannot do any other useful work while waiting for the device.
Interrupts: A Smarter Signal
To avoid the waste of polling, hardware uses Interrupts. When a device is done with a task, it sends a high-voltage signal across a dedicated wire (the Interrupt-Request Line).
The CPU immediately pauses its current instruction, looks up the correct 'Interrupt Handler' code in an Interrupt Vector Table, executes the I/O cleanup, and then resumes its previous work.
Direct Memory Access (DMA)
For massive data transfers (like reading a 4GB movie file from disk), using interrupts for every few bytes is still too slow for the CPU. Instead, we use a DMA Controller.
The CPU tells the DMA: 'Move 1 million bytes from disk address X to RAM address Y.' The CPU then goes back to running user programs. The DMA handles the transfer autonomously and sends a *single* interrupt only once the entire 1 million bytes have been moved.
I/O Hardware Logic
Question 1 of 1Test your understanding of hardware-level I/O communication.